Technology

Gate

Isolation

Metal

ECC
(V)

Min. Line

(mm)

Note

P-MOS

Al

 

1

7¼14

4

Loading transistors
with built-in channel

CMOS

Poly-Si

LOCOS

1-2

1.5¼5

1.2

 

CMOS

2 poly-Si

LOCOS

1

5

2.5

 

CMOS

Floating
poly-Si

LOCOS

1

5

2.5

For EEPROM
with UV erasing

CMOS

Floating
poly-Si

LOCOS

1

5

2.5

For EEPROM
with electrical erasing

High voltage CMOS

Poly-Si

LOCOS

1

15

4

 

Technology

Epitaxy
(
mm)

Isolation

Metal

ECC
(V)

Min. Line (mm)

Note

Bipolar

5¼17

Diffusion

1¼2

5¼40

3

 

Bipolar

1.5¼5

Isoplanar I, II

1¼2

7¼10

1.5